Standard load control devices, such as electric light dimmers, use one or more semiconductor switches, such as triacs or field-effect transistors (FETs), to control the current delivered to an electric load, for example, to control the intensity of a lighting load. The semiconductor switch is typically coupled in series between an alternating-current (AC) source and the lighting load. Using a phase-control dimming technique, the dimmer renders the semiconductor switch conductive for a portion of each half-cycle to provide power to the lighting load, and renders the semiconductor switch non-conductive for the other portion of the half-cycle to disconnect power from the load. In forward phase-control dimming, the semiconductor switch is conductive at the end of each half-cycle. Alternatively, in reverse-phase control dimming, the semiconductor switch is conductive at the beginning of each half-cycle.
FIG. 1 is a simplified schematic diagram of a prior art dimmer 10. The dimmer 10 has a hot connection H to an AC source 12 and a dimmed hot connection DH to a lighting load 14. The dimmer 10 comprises two FETs 16, 18 connected in anti-series connection between the AC source 12 and the lighting load 14 to control the amount of power delivered to the load. The FETs 16, 18 each have control inputs (or gates) that are coupled to a control circuit 20, such as a microcontroller. The control circuit 20 is operable to render each FET 16, 18 conductive (or non-conductive) by providing (or not providing) to the gate a voltage greater than the gate threshold voltage VTH of the FET. The gates of the FETs 16, 18 are often tied together to allow for a simplified operation of the FETs. The resulting operation allows for one FET 16 to block the flow of current to the load 14 during the positive half-cycles and the second FET 18 to block the flow of current to the load 14 during the negative half-cycles of the AC source.
A power supply 22 generates a direct-current (DC) voltage VCC to power the control circuit 20. A zero-cross circuit 24 provides an indication of the zero-crossings of the AC voltage of the AC source 12 to the control circuit 20. A zero-crossing is defined as the time at which the AC supply voltage transitions from positive to negative polarity, or from negative to positive polarity, at the beginning of each half-cycle. The zero-cross circuit 24 receives the AC voltage through a diode D1 in the positive half-cycles and through a diode D2 in the negative half-cycles. The control circuit 20 determines when to turn on or off the FETs 16, 18 each half-cycle by timing from each zero-crossing of the AC voltage.
A majority of the power dissipation (or “power loss”) in the FETs 16, 18 of the dimmer 10 occurs during two main time periods of each half-cycle: a conduction time, tCONDUCT, and a switching time, tSWITCH. During the conduction time, a conduction loss, PD-CONDUCT, occurs and is determined by the on-resistance, RDS(on), of the FETs and the load current, ILOAD, through the FETs, i.e.,PD-CONDUCT=ILOAD2·RDS(on).  (Equation 1)During the switching time tSWITCH, one of the FETs 16, 18 will transition between the non-conductive and conductive states. FIG. 2 shows waveforms of the current ID through the FET, voltage VDS across the FET, and the instantaneous power dissipation PD-INST of the FET during the switching time tSWITCH when the dimmer 10 is operating with reverse-phase control dimming. As shown in FIG. 2, the FET will transition from a conductive state to a non-conductive state during the switching time. Accordingly, the current ID through the FET will decrease while the voltage VDS across the FET will increase during the switching time tSWITCH. On the other hand, with forward-phase control dimming, the FET will transition from a non-conductive state to a conductive state during the switching time tSWITCH, and thus, the current ID through the FET will increase and the voltage VDS across the FET will decrease.
A switching loss, PD-SWITCH, occurs during the switching time and is dependent on the falling current ID and the rising voltage VDS (or the rising current ID and the falling voltage VDS) during the switching time tSWITCH. Thus, the total power PD-TOTAL dissipated by the FETs 16, 18 is dependent on the conduction loss during the conduction time and the switching loss during the switching time, i.e.,PD-TOTAL=(tCONDUCT·PD-CONDUCT+tSWITCH·PD-SWITCH)/THALF-CYCLE,  (Equation 2)where THALF-CYCLE is the period of a half-cycle. The overlap of the changing current IDS and the changing voltage VDS causes the instantaneous power dissipation PD-INST to peak up during the switching time tSWITCH as shown in FIG. 2. The switching loss PD-SWITCH is typically a significant portion of the total power dissipation PD-TOTAL. Accordingly, a small increase in the switching time tSWITCH can cause a significant rise in the total power dissipation PD-TOTAL of the FETs.
Lighting dimmers are regulated by many industry standards, for example, electromagnetic interference (EMI) standards that limit the magnitude of the EMI noise that exists on the phase-control output of the dimmer. If the switching time tSWITCH, i.e., the time when the semiconductor switch changes from the conductive state to the nonconductive state (and vice versa), is substantially short, the phase-control output will have many high-frequency components and the EMI noise will be increased. Therefore, many prior art dimmers have included a gate resistor RG in series with the gates of the FETs to slow down, i.e., increase, the rise and fall times of the current flowing through the FET during these switching times. For example, if the resistance of the gate resistor RG is 22 kΩ, the switching time tSWITCH may be approximately 62 μsec when the AC source voltage has a magnitude of 240 VAC, the load current drawn by the lighting load has a magnitude of 10 A, and the ambient temperature is 25° C.
However, the increased switching times tSWITCH due to the gate resistor RG lead to an increased total power dissipation PD-TOTAL of the FET (as shown in Equation 2 above). Further, as the power dissipation PD-TOTAL of the FET increases and the temperature of the FET rises, the on-resistance RDS(on) will increase, which then leads to an increased conduction loss PD-CONDUCT.
Compounding this thermal issue is the fact that the rising temperature causes the internal characteristics of the FET to change such that the threshold voltage VTH of the FET decreases. To transition the FETs 16, 18 from the conductive state to the non-conductive state, the control circuit 20 pulls the control inputs of the FETs towards circuit common. Accordingly, a gate current IG will flow out of the gate and will have a magnitude ofIG=VTH/RG=CM·Δv/Δt,  (Equation 3)where CM is the Miller capacitance of the FET, Δt equals the switching time tSWITCH, and Δv is the changing voltage at the gate of the FET. Because of the rising voltage across the FET and the falling current through the FET, the voltage at the gate of the FET, i.e., Δv, will remain substantially constant at the threshold voltage VTH for the duration of the switching time tSWITCH. Therefore, the switching time tSWITCH is dependent on the threshold voltage VTH, sincetSWITCH=Δt=(RG·CM·Δv)VTH.  (Equation 4)Thus, as the temperature of the FET rises, the threshold voltage VTH of the FET decreases, the switching time tSWITCH increases (e.g., above 85 μsec) and the total power dissipation PD-TOTAL increases. This condition can lead to a thermal runaway situation, which causes undesirable device temperatures and, ultimately, failure of the FETs (for example, when the temperature of the FETs rises to 135° C.).
Some prior art dimmers decrease the conduction time of the FETs each half-cycle in order to decrease the conduction loss PD-CONDUCT as the temperature of the FETs increases. However, this causes the intensity level of the lighting load to change, which is undesirable. Thus, there exists a need for a gate drive circuit which allows for an increased switching time, and thus minimal EMI noise, when the FETs are operating at or near room temperature, and which further provides a decreased switching time when the temperature of the FETs has increased to prevent overheating of the FETs.